Renesas公司的ISL70005SEH和ISL73005SEH是抗辐射双输出点负载集成的同步降压和低压降稳压器,包括了高效率同步降压稳压器和低噪音低压降(LDO)稳压器.降压稳压器采用兵电压模式控制架构,采用电阻可调整的开关频率在100kHz到1MHz.外接可调整的回路补偿在稳定性和输出动态范围间达到最佳.内部同步功率开关优化了高效率和极好的热性能.LDO完全独立于开关稳压器进行配置.它采用NMOS通过器件和单独芯片偏压电压(L_VCC)来驱动它的栅极,使得LDO在L_VIN输入工作在非常低的电压.LDO沉和源电流连续为1A,使它非常适合给DDR存储器供电.工作温度-55℃到+125℃,主要用在低功耗FPGA核,辅助和I/O电源的点负载(POL),DDR存储器电源VDDQ和VTT轨,卫星载荷的分布使电源系统.本文介绍了ISL70005SEH主要特性,DDR2存储器电源解决方案和应用电路图,以及评估板ISL70005SEHDEMO1Z主要特性,框图,电路图,材料清单和PCB设计图.
The ISL70005SEH and ISL73005SEH are radiation hardened dual output Point-of-Load (POL) regulators combining the high efficiency of a synchronous buck regulator with the low noise of a Low Dropout (LDO) regulator. They are suited for systems with 3.3V or 5V power buses and can support continuous output load currents of 3A for the buck regulator and ±1A for the LDO.
The buck regulator uses a voltage mode control architecture and switches at a resistor adjustable frequencyof 100kHz to 1MHz. Externally adjustable loop compensation allows for an optimum balance between stability and output dynamic performance.The internal synchronous power switches are optimized for high efficiency and excellent thermal performance.
The LDO is completely configurable independent of the switching regulator. It uses NMOS pass devices and separate chip bias voltage (L_VCC) to drive its gate, enabling the LDO to operate with a very low voltage at the L_VIN input. The LDO can sink and source up to 1A continuously, making it an ideal choice to power DDR memory.
The ISL70005SEH and ISL73005SEH are available in a space saving 28 Ld ceramic dual flat-pack package or in die form. They are specified to operate across a temperature range of TA = -55℃ to +125℃.
ISL70005SEH主要特性:
• Dual output regulator: sync buck and LDO
• Independent EN, SS, and PG indicators
• ±1% reference voltage
• 1A current sourcing/sinking capability on LDO
• External clock synchronization: 100kHz to 1MHz
• Full military temperature range operation
○ TA = -55℃ to +125℃
○ TJ = -55℃ to +150℃
• Radiation acceptance testing - ISL70005SEH
○ HDR (50-300rad(Si)/s): 100krad(Si)
○ LDR (0.01rad(Si)/s): 75krad(Si)
• Radiation acceptance testing - ISL73005SEH
○ LDR (0.01rad(Si)/s): 75krad(Si)
• SEE hardness (see test report)
○ No SEB or SEL at LET 86.4MeV•cm2/mg
○ SET at LET 86.4MeV•cm2/mg
○ No SEFI at LET 43MeV•cm2/mg
• Electrically screened to DLA SMD 5962-19209
ISL70005SEH应用:
• Point-of-load for low power FPGA core, auxiliary and I/O supply voltages
• DDR memory power for VDDQ and VTT rails
• Distributed power system of satellite payloads
图1.DDR2存储器电源解决方案
图2.ISL70005SEH框图
图3.ISL70005SEH低功耗FPGA核和I/O电源应用电路图
图4.ISL70005SEH DDR存储器电源应用电路图
ISL70005SEH应用:
Point-of-load for low power FPGA core, auxiliary and I/O supply voltages
DDR memory power for VDDQ and VTT rails
Distributed power system of satellite payloads
评估板ISL70005SEHDEMO1Z
The ISL70005SEHDEMO1Z demonstration board is designed to demonstrate the performance of the ISL70005SEH 3A buck regulator and 1A source/sink LDO. The demo board is specifically configured for the DDR Memory VDDQ and VTT supply rail applications. The buck regulator output voltage is pin jumper selectable for 1.5V, 1.8V, and 2.5V. The LDO output voltage is configured to track ½ the buck regulator output voltage. The ISL70005SEHDEMO1Z only requires one input supply voltage at the PVIN terminal for operation. The PVIN accepts an input voltage range of 3V to 5.5V.
评估板ISL70005SEHDEMO1Z主要特性:
• Dual point-of-load regulator: 3A buck and 1A source/sink LDO
• Fully independent enable, soft-start, and power-good indicator
• 3V to 5.5V operating voltage
• Configured for LDO tracking buck application (such as DDR memory) Specifications
• Analog and buck regulator input voltage range (PVIN): 3V to 5.5V
• Buck output voltage selection: 2.5V (DDR), 1.8V (DDR2), or 1.5V (DDR3)
• Maximum buck output current: 3A
• Buck preset switching frequency: 1MHz
• LDO input voltage (L_VIN) range: 1.0V to PVIN
• LDO output voltage tracks 1/2 of buck VOUT
• Maximum LDO output (L_OUT) current: 1A sourcing or 1A sinking
• Board dimension: 11cm width x 7.5cm height
• Board layers: Four
• Board PCB copper weight: 2oz.
• Board revision: A
图5.评估板ISL70005SEHDEMO1Z框图
图6.评估板ISL70005SEHDEMO1Z外形图(正面)
图7.评估板ISL70005SEHDEMO1Z外形图(背面)
图8.评估板ISL70005SEHDEMO1Z电路图
评估板ISL70005SEHDEMO1Z材料清单:
图9.评估板ISL70005SEHDEMO1Z PCB设计图:顶层丝印
图10.评估板ISL70005SEHDEMO1Z PCB设计图:顶层
图11.评估板ISL70005SEHDEMO1Z PCB设计图:层2
图12.评估板ISL70005SEHDEMO1Z PCB设计图:层3
图13.评估板ISL70005SEHDEMO1Z PCB设计图:底层
图14.评估板ISL70005SEHDEMO1Z PCB设计图:底层丝印
详情请见:
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