Renesas公司的ISL70005SEH和ISL73005SEH是抗輻射雙輸出點負載集成的同步降壓和低壓降穩壓器,包括了高效率同步降壓穩壓器和低噪音低壓降(LDO)穩壓器.降壓穩壓器採用兵電壓模式控制架構,採用電阻可調整的開關頻率在100kHz到1MHz.外接可調整的迴路補償在穩定性和輸出動態範圍間達到最佳.內部同步功率開關優化了高效率和極好的熱性能.LDO完全獨立於開關穩壓器進行配置.它採用NMOS通過器件和單獨芯片偏壓電壓(L_VCC)來驅動它的柵極,使得LDO在L_VIN輸入工作在非常低的電壓.LDO沉和源電流連續為1A,使它非常適合給DDR存儲器供電.工作溫度-55℃到+125℃,主要用在低功耗FPGA核,輔助和I/O電源的點負載(POL),DDR存儲器電源VDDQ和VTT軌,衛星載荷的分佈使電源系統.本文介紹了ISL70005SEH主要特性,DDR2存儲器電源解決方案和應用電路圖,以及評估板ISL70005SEHDEMO1Z主要特性,框圖,電路圖,材料清單和PCB設計圖.
The ISL70005SEH and ISL73005SEH are radiation hardened dual output Point-of-Load (POL) regulators combining the high efficiency of a synchronous buck regulator with the low noise of a Low Dropout (LDO) regulator. They are suited for systems with 3.3V or 5V power buses and can support continuous output load currents of 3A for the buck regulator and ±1A for the LDO.
The buck regulator uses a voltage mode control architecture and switches at a resistor adjustable frequencyof 100kHz to 1MHz. Externally adjustable loop compensation allows for an optimum balance between stability and output dynamic performance.The internal synchronous power switches are optimized for high efficiency and excellent thermal performance.
The LDO is completely configurable independent of the switching regulator. It uses NMOS pass devices and separate chip bias voltage (L_VCC) to drive its gate, enabling the LDO to operate with a very low voltage at the L_VIN input. The LDO can sink and source up to 1A continuously, making it an ideal choice to power DDR memory.
The ISL70005SEH and ISL73005SEH are available in a space saving 28 Ld ceramic dual flat-pack package or in die form. They are specified to operate across a temperature range of TA = -55℃ to +125℃.
ISL70005SEH主要特性:
• Dual output regulator: sync buck and LDO
• Independent EN, SS, and PG indicators
• ±1% reference voltage
• 1A current sourcing/sinking capability on LDO
• External clock synchronization: 100kHz to 1MHz
• Full military temperature range operation
○ TA = -55℃ to +125℃
○ TJ = -55℃ to +150℃
• Radiation acceptance testing - ISL70005SEH
○ HDR (50-300rad(Si)/s): 100krad(Si)
○ LDR (0.01rad(Si)/s): 75krad(Si)
• Radiation acceptance testing - ISL73005SEH
○ LDR (0.01rad(Si)/s): 75krad(Si)
• SEE hardness (see test report)
○ No SEB or SEL at LET 86.4MeV•cm2/mg
○ SET at LET 86.4MeV•cm2/mg
○ No SEFI at LET 43MeV•cm2/mg
• Electrically screened to DLA SMD 5962-19209
ISL70005SEH應用:
• Point-of-load for low power FPGA core, auxiliary and I/O supply voltages
• DDR memory power for VDDQ and VTT rails
• Distributed power system of satellite payloads
圖1.DDR2存儲器電源解決方案
圖2.ISL70005SEH框圖
圖3.ISL70005SEH低功耗FPGA核和I/O電源應用電路圖
圖4.ISL70005SEH DDR存儲器電源應用電路圖
ISL70005SEH應用:
Point-of-load for low power FPGA core, auxiliary and I/O supply voltages
DDR memory power for VDDQ and VTT rails
Distributed power system of satellite payloads
評估板ISL70005SEHDEMO1Z
The ISL70005SEHDEMO1Z demonstration board is designed to demonstrate the performance of the ISL70005SEH 3A buck regulator and 1A source/sink LDO. The demo board is specifically configured for the DDR Memory VDDQ and VTT supply rail applications. The buck regulator output voltage is pin jumper selectable for 1.5V, 1.8V, and 2.5V. The LDO output voltage is configured to track ½ the buck regulator output voltage. The ISL70005SEHDEMO1Z only requires one input supply voltage at the PVIN terminal for operation. The PVIN accepts an input voltage range of 3V to 5.5V.
評估板ISL70005SEHDEMO1Z主要特性:
• Dual point-of-load regulator: 3A buck and 1A source/sink LDO
• Fully independent enable, soft-start, and power-good indicator
• 3V to 5.5V operating voltage
• Configured for LDO tracking buck application (such as DDR memory) Specifications
• Analog and buck regulator input voltage range (PVIN): 3V to 5.5V
• Buck output voltage selection: 2.5V (DDR), 1.8V (DDR2), or 1.5V (DDR3)
• Maximum buck output current: 3A
• Buck preset switching frequency: 1MHz
• LDO input voltage (L_VIN) range: 1.0V to PVIN
• LDO output voltage tracks 1/2 of buck VOUT
• Maximum LDO output (L_OUT) current: 1A sourcing or 1A sinking
• Board dimension: 11cm width x 7.5cm height
• Board layers: Four
• Board PCB copper weight: 2oz.
• Board revision: A
圖5.評估板ISL70005SEHDEMO1Z框圖
圖6.評估板ISL70005SEHDEMO1Z外形圖(正面)
圖7.評估板ISL70005SEHDEMO1Z外形圖(背面)
圖8.評估板ISL70005SEHDEMO1Z電路圖
評估板ISL70005SEHDEMO1Z材料清單:
圖9.評估板ISL70005SEHDEMO1Z PCB設計圖:頂層絲印
圖10.評估板ISL70005SEHDEMO1Z PCB設計圖:頂層
圖11.評估板ISL70005SEHDEMO1Z PCB設計圖:層2
圖12.評估板ISL70005SEHDEMO1Z PCB設計圖:層3
圖13.評估板ISL70005SEHDEMO1Z PCB設計圖:底層
圖14.評估板ISL70005SEHDEMO1Z PCB設計圖:底層絲印
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